Pin | Name | Direction | Color | Description |
1 | | | | +5V 3-T regulator voltage supply (about +8V) |
1 | | | | +5V 3-T regulator voltage supply (about +8V) |
1 | | | | +5V 3-T regulator voltage supply (about +8V) |
2 | - | Dito | | |
2 | - | Dito | | |
2 | - | Dito | | |
3 | GND | - | | Ground |
3 | GND | - | | Ground |
3 | GND | - | | Ground |
4 | READYA | - | | System ready (10K pull-up to +5V) |
4 | READYA | - | | System ready (10K pull-up to +5V) |
4 | READYA | - | | System ready (10K pull-up to +5V) |
5 | GND | - | | Ground |
5 | GND | - | | Ground |
5 | GND | - | | Ground |
6 | RESET* | OUT | | System reset (active low) |
6 | RESET* | OUT | | System reset (active low) |
6 | RESET* | OUT | | System reset (active low) |
7 | GND | - | | Ground |
7 | GND | - | | Ground |
7 | GND | - | | Ground |
8 | SCLK | nc | | System clock (not connected) |
8 | SCLK | nc | | System clock (not connected) |
8 | SCLK | nc | | System clock (not connected) |
9 | LCP* | nc | | CPU indicator 1=TI99 0=2nd generation (not connected) |
9 | LCP* | nc | | CPU indicator 1=TI99 0=2nd generation (not connected) |
9 | LCP* | nc | | CPU indicator 1=TI99 0=2nd generation (not connected) |
10 | AUDIO | IN | | Input audio (=AUDIOIN) |
10 | AUDIO | IN | | Input audio (=AUDIOIN) |
10 | AUDIO | IN | | Input audio (=AUDIOIN) |
11 | RDBENA* | IN | | Active low: enable flex cable data bus drivers (1K pull-up) |
11 | RDBENA* | IN | | Active low: enable flex cable data bus drivers (1K pull-up) |
11 | RDBENA* | IN | | Active low: enable flex cable data bus drivers (1K pull-up) |
12 | PCBEN | H | | PCB enable for burn-in (always High) |
12 | PCBEN | H | | PCB enable for burn-in (always High) |
12 | PCBEN | H | | PCB enable for burn-in (always High) |
13 | HOLD* | H | | Active low CPU hold request (always High) |
13 | HOLD* | H | | Active low CPU hold request (always High) |
13 | HOLD* | H | | Active low CPU hold request (always High) |
14 | IAQHA | nc | | IAQ [or] HOLDA (logical or) |
14 | IAQHA | nc | | IAQ [or] HOLDA (logical or) |
14 | IAQHA | nc | | IAQ [or] HOLDA (logical or) |
15 | SENILA* | H | | Interrupt level A sense enable (always High) |
15 | SENILA* | H | | Interrupt level A sense enable (always High) |
15 | SENILA* | H | | Interrupt level A sense enable (always High) |
16 | SENILB* | H | | Interrupt level B sense enable (always High) |
16 | SENILB* | H | | Interrupt level B sense enable (always High) |
16 | SENILB* | H | | Interrupt level B sense enable (always High) |
17 | INTA* | IN | | Active low interrupt level A (=EXTINT*) |
17 | INTA* | IN | | Active low interrupt level A (=EXTINT*) |
17 | INTA* | IN | | Active low interrupt level A (=EXTINT*) |
18 | LOAD* | nc | | Unmaskable interrupt (not connected) |
18 | LOAD* | nc | | Unmaskable interrupt (not connected) |
18 | LOAD* | nc | | Unmaskable interrupt (not connected) |
19 | D7 | IN/OUT | | Data bus, bit 7 (least significant) |
19 | D7 | IN/OUT | | Data bus, bit 7 (least significant) |
19 | D7 | IN/OUT | | Data bus, bit 7 (least significant) |
20 | GND | - | | Ground |
20 | GND | - | | Ground |
20 | GND | - | | Ground |
21 | D5 | IN/OUT | | |
21 | D5 | IN/OUT | | |
21 | D5 | IN/OUT | | |
22 | D6 | IN/OUT | | |
22 | D6 | IN/OUT | | |
22 | D6 | IN/OUT | | |
23 | D3 | IN/OUT | | |
23 | D3 | IN/OUT | | |
23 | D3 | IN/OUT | | |
24 | D4 | IN/OUT | | |
24 | D4 | IN/OUT | | |
24 | D4 | IN/OUT | | |
25 | D1 | IN/OUT | | |
25 | D1 | IN/OUT | | |
25 | D1 | IN/OUT | | |
26 | D2 | IN/OUT | | |
26 | D2 | IN/OUT | | |
26 | D2 | IN/OUT | | |
27 | GND | - | | Ground |
27 | GND | - | | Ground |
27 | GND | - | | Ground |
28 | D0 | IN/OUT | | Data bus, bit 0 (most significant) |
28 | D0 | IN/OUT | | Data bus, bit 0 (most significant) |
28 | D0 | IN/OUT | | Data bus, bit 0 (most significant) |
29 | A14 | OUT | | |
29 | A14 | OUT | | |
29 | A14 | OUT | | |
30 | A15 | OUT | | Address bus, lsb. Also CRU output bit. |
30 | A15 | OUT | | Address bus, lsb. Also CRU output bit. |
30 | A15 | OUT | | Address bus, lsb. Also CRU output bit. |
31 | A12 | OUT | | |
31 | A12 | OUT | | |
31 | A12 | OUT | | |
32 | A13 | OUT | | |
32 | A13 | OUT | | |
32 | A13 | OUT | | |
33 | A10 | OUT | | |
33 | A10 | OUT | | |
33 | A10 | OUT | | |
34 | A11 | OUT | | |
34 | A11 | OUT | | |
34 | A11 | OUT | | |
35 | A8 | OUT | | |
35 | A8 | OUT | | |
35 | A8 | OUT | | |
36 | A9 | OUT | | |
36 | A9 | OUT | | |
36 | A9 | OUT | | |
37 | A6 | OUT | | |
37 | A6 | OUT | | |
37 | A6 | OUT | | |
38 | A7 | OUT | | |
38 | A7 | OUT | | |
38 | A7 | OUT | | |
39 | A4 | OUT | | |
39 | A4 | OUT | | |
39 | A4 | OUT | | |
40 | A5 | OUT | | |
40 | A5 | OUT | | |
40 | A5 | OUT | | |
41 | A2 | OUT | | |
41 | A2 | OUT | | |
41 | A2 | OUT | | |
42 | A3 | OUT | | |
42 | A3 | OUT | | |
42 | A3 | OUT | | |
43 | A0 | OUT | | Address but, bit 0 (most significant) |
43 | A0 | OUT | | Address but, bit 0 (most significant) |
43 | A0 | OUT | | Address but, bit 0 (most significant) |
44 | A1 | OUT | | |
44 | A1 | OUT | | |
44 | A1 | OUT | | |
45 | AMB | H | | Extra address bit. Always High. |
45 | AMB | H | | Extra address bit. Always High. |
45 | AMB | H | | Extra address bit. Always High. |
46 | AMA | H | | Extra address bit. Always High. |
46 | AMA | H | | Extra address bit. Always High. |
46 | AMA | H | | Extra address bit. Always High. |
47 | GND | - | | Ground |
47 | GND | - | | Ground |
47 | GND | - | | Ground |
48 | AMC | H | | Extra address bit. Always High. |
48 | AMC | H | | Extra address bit. Always High. |
48 | AMC | H | | Extra address bit. Always High. |
49 | GND | - | | Ground |
49 | GND | - | | Ground |
49 | GND | - | | Ground |
50 | CLKOUT* | OUT | | Inversion of phase 3 clock (=PHI3*) |
50 | CLKOUT* | OUT | | Inversion of phase 3 clock (=PHI3*) |
50 | CLKOUT* | OUT | | Inversion of phase 3 clock (=PHI3*) |
51 | CRUCLK* | OUT | | Inversion of TMS9900 CRUCLOCK pin |
51 | CRUCLK* | OUT | | Inversion of TMS9900 CRUCLOCK pin |
51 | CRUCLK* | OUT | | Inversion of TMS9900 CRUCLOCK pin |
52 | DBIN | OUT | | Active high = read memory |
52 | DBIN | OUT | | Active high = read memory |
52 | DBIN | OUT | | Active high = read memory |
53 | GND | - | | Ground |
53 | GND | - | | Ground |
53 | GND | - | | Ground |
54 | WE* | OUT | | Write Enable (derived from TMS9900 WE* pin) |
54 | WE* | OUT | | Write Enable (derived from TMS9900 WE* pin) |
54 | WE* | OUT | | Write Enable (derived from TMS9900 WE* pin) |
55 | CRUIN | IN | | CRU input bit to TMS9900 |
55 | CRUIN | IN | | CRU input bit to TMS9900 |
55 | CRUIN | IN | | CRU input bit to TMS9900 |
56 | MEMEN* | OUT | | Memory access enable (active low) |
56 | MEMEN* | OUT | | Memory access enable (active low) |
56 | MEMEN* | OUT | | Memory access enable (active low) |
57 | | | | -12 Volts 3-T regulator supply voltage (about -16V) |
57 | | | | -12 Volts 3-T regulator supply voltage (about -16V) |
57 | | | | -12 Volts 3-T regulator supply voltage (about -16V) |
58 | | | | Dito |
58 | | | | Dito |
58 | | | | Dito |
59 | | | | +12 Volts 3-T regulator supply voltage (about +16V) |
59 | | | | +12 Volts 3-T regulator supply voltage (about +16V) |
59 | | | | +12 Volts 3-T regulator supply voltage (about +16V) |
60 | | | | Dito |
60 | | | | Dito |
60 | | | | Dito |